@conference {761, title = {Implementing an ISR defense on a MIPS architecture}, booktitle = {2017 XLIII Latin American Computer Conference (CLEI)}, year = {2017}, month = {09/2017}, publisher = {IEEE}, organization = {IEEE}, address = {C{\'o}rdoba., Argentina}, abstract = {

Code injection attacks are an undeniable threat in today{\textquoteright}s cyberworld. Instruction Set Randomization (ISR) was initially proposed in 2003. This technique was designed to protect systems against code injection attacks by creating an unique instruction set for each machine, thanks to randomization. It is a promising technique in the growing embedded system and Internet of Things (IoT) devices ecosystem, where the lack of complex memory management make these devices more vulnerable. However, most of ISR implementations up to day are entirely software based. In this work, we implement hardware support for an ISR defense on an 32 bits, 5 pipeline stages MIPS processor (which is an embedded system compatible architecture). Two obfuscation schemes were implemented, one based on XOR encryption and the other on transposition. The hardware implementation was tested under synthetic code injection attacks and results shows the effectiveness of the defense using both encryption circuits.

}, keywords = {code injection attacks, complex memory management, cryptography, embedded system, embedded systems, Encryption, encryption circuits, Hardware, Instruction Set Randomization, instruction sets, integrated circuit design, integrated circuit testing, Internet of Things devices ecosystem, IoT, ISR, ISR defense, microprocessor chips, microprocessor without interlocked pipeline stages, MIPS processor, Pipelines, security of data, Silicon compounds, synthetic code injection attacks, XOR encryption}, isbn = {978-1-5386-3057-0}, doi = {10.1109/CLEI.2017.8226448}, url = {http://ieeexplore.ieee.org/document/8226448/}, author = {L. S. Sancho and E. G. Barrantes} } @conference {576, title = {An applied methodology for information security and assurance: A study case for cloud computing}, booktitle = {Internet Technology and Secured Transactions (ICITST), 2014 9th International Conference for}, year = {2014}, month = {12/2014}, abstract = {

Information security is one of the main concerns in many fields of computer and information technologies, and even more on new emerging technologies such as cloud computing. Current security standards and models usually focus on "what" has to be done about security, but they do not propose "how" to deal with the inherent complexity of assuring modern infrastructures. Security standards usually produce large check lists describing security countermeasures, but they lack a comprehensive and complete process to define the security requirements of information being managed. As a consequence, security implementations may miss important security controls, and they cannot guarantee a consistent and in-depth security implementation at the different layers of the system. We propose a methodology with a novel hierarchical approach to guide a comprehensive and complete assurance process. Real use cases are shown, by applying our methodology to assure a private cloud being developed at the Universidad de Costa Rica (UCR).

}, keywords = {cloud computing, Computational modeling, Hardware, information security, Servers, Standards}, doi = {10.1109/ICITST.2014.7038851}, author = {Villalon-Fonseca, R. and Solano-Rojas, B.J. and Marin-Raventos, G.} } @conference {706, title = {Known/chosen key attacks against software instruction set randomization}, booktitle = {Computer Security Applications Conference, 2006. ACSAC{\textquoteright}06. 22nd Annual}, year = {2006}, month = {12/2006}, publisher = {IEEE}, organization = {IEEE}, address = {Miami, FL, Estados Unidos}, abstract = {

Instruction set randomization (ISR) has been proposed as a form of defense against binary code injection into an executing program. One proof-of-concept implementation is randomized instruction set emulator (RISE), based on the open-source Valgrind IA-32 to IA-32 binary translator. Although RISE is effective against attacks that are not RISE-aware, it is vulnerable to pure data and hybrid data-code attacks that target its data, as well to some classes of brute-force guessing. In order to enable the design of a production version, we describe implementation-specific and generic vulnerabilities that can be used to overcome RISE in its current form. We present and discuss attacks and solutions in three categories: known-key attacks that rely on the key being leaked and then used to pre-scramble the attacking code; chosen-key attacks that use implementation weaknesses to allow the attacker to define its own key, or otherwise affect key generation; and key-guessing ("brute-force") attacks, about which we explore the design of mini-malistic loaders which can be used to minimize the number of mask bytes required for a successful key-guessing attack. All the described attacks were tested in real-world scenarios

}, keywords = {Binary codes, Computer aided instruction, Emulation, genetics, Hardware, Open source software, Production, Protection, Security, Testing}, isbn = {0-7695-2716-7}, doi = {10.1109/ACSAC.2006.33}, url = {http://ieeexplore.ieee.org/document/4041180/}, author = {Weiss, Yoav and Barrantes, Elena Gabriela} }